Full wave phase sensitive demodulators

ABSTRACT

The alternating current signal to be demodulated is applied to a resistive voltage divider which provides two alternating current voltages. An NPN transistor and a PNP transistor are connected to the voltage divider and are alternately rendered conductive during half cycles of the alternating current voltages so that one transistor passes alternate half cycles of one voltage and the other transistor passes the other alternate half cycles of the other voltage. The passed voltages are combined to provide a full wave demodulated output corresponding in polarity to the phase of the alternating current voltage.

United States Patent Parfomak et al.

[451 Apr. 25, 1972 FULL WAVE PHASE SENSITIVE I DEMODULATORS Inventors: Walter Parfomak, Wallington; George Antipas, West New York, both of NJ.

The Bendix Corporation Mar. 9, 1970 Assignee:

Filed:

Appl. No.:

US. Cl ..329/l01, 307/235, 307/249, 329/166, 330/13 Int. Cl. ..H03d 1/18 Field of Search ..329/l0l 103, 166; 307/249, 307/235; 330/13, 15; 332/43 B References Cited UNITED STATES PATENTS l/l968 Jensen ..329/l0l l/l958 Greefkes ..332/43BX PNP TRANSISTOR I2 3,329,910 7/1967 Moses ..332/43BX 2,963,655 12/1960 Schrock.. .....330/l5X 3,517,267 6/1970 Ferrieu ..329/l66 X Primary Examiner-Alfred L. Brody Attorney-Ronald G. Gillespie and Flame, Arens, Hartz, Smith and Thompson [5 7] ABSTRACT cles of the other voltage. The passed voltages are combined to provide a full wave demodulated output corresponding in polarity to the phase of the alternating current voltage.

1 Claims, 6 Drawing Figures PHASE SENSITIVE DEMODULATOR FULL WAVE SIGNAL NPN TRANSISTOR 22 FIG. 2?

Elk-2W PATENTED S 3,659,215

PHASE SENS/T/vE DEMODULATORJ PNP TRANSISTOR 2 2 l4 l6 FULL wAvE E; SIGNAL FIG.1-

NPN TRANSISTOR 22 INVEN'I'ORS WALTER PA RFOMAK BY GEORGE ANT/PAS ATT NEY BACKGROUND OF THE INVENTION tor to have a slow response time and frequencylimitations,

The similar type transistors required a a separate biasing voltage for each transistor. I

The device of the present invention uses a resistive voltage divider to improve response time and avoid frequency limitations. The use of transistors of different types which may be controlled by a single biasing voltage reduces power consumption.

SUM-MARY or THE INVENTION A phase sensitive demodulator for demodulating an alternating current signal comprising means for dividing the alternating current signal into two alternating current voltages and having a connection common to both voltages. An output terminal is connected to the common connection of the dividing means. NPN and PNP type transistors are connected between the dividing means and the second output terminal. The transistors are alternately rendered conducting in alternate half cycles of. the voltages and pass one of the voltages from the dividing means to the output terminals in alternate half cycles when one transistor conducts and for passing the other voltage from the dividing means to the output terminals in the other alternate half cycle when the other transistor conducts to provide a demodulated output across the output terminals corresponding in polarity to the phase of the alternating current signal.

One object of the present invention is to provide a phase sensitive demodulator which demodulates an alternating current signal and provides a full wave demodulated output. 7

Another object of the present invention is to divide an alternating current signal to provide two signals so that half cycles of the two signals may be combined to provide a full wave demodulated signal.

Another object of the present invention is to provide a full wave phase sensitivedemodulator having no reactive elements so as to have an unlimited frequency response and a fast response time. i I

Another object of the present invention is to use an NPN transistor and a PNP transistor controlled by a simple alternating current bias phase related to an alternating current signal to be demodulated.

The foregoing and other objects and advantages of the invention will appear more fully hereinafter from a consideration of the detailed description which'follows, taken together with the accompanying drawings wherein one embodiment of the invention is illustrated by way'of example. It is to be expressly understood, however, that the drawings are for illustration purposes only and are not to be construed as defining the limits of the invention.

DESCRIPTION OF THE DRAWINGS FIG. 1 shows a schematic diagram of a full wave phase sensitive demodulator constructed in accordance with the present invention.

FIGS. 2A through 2E are diagrammatic representations of voltages occurring during operation of the phase sensitive demodulator shown in FIG. I.

DESCRIPTION OF THE INVENTION Referring to FIG. I. a phase sensitive demodulator constructcd according to the invention, is shown as comprising a resistive voltage divider including resistor 5 and 6 having a common connection 8 and connected in series across a signal source which provides an alternating current signal source E,,

shown in FIG. 2A, to be demodulated. Resistors 5, 6 provide two alternating current voltage E and E, in phase with signal In FIG. 1, an output terminal 13 is connected to common connection 8. A PNPtransistor 12 has a collector 14 connected to a terminal 2sand an emitter- 16 connected to a second output terminal 17. An NPN transistor 22 has a collector 24 connected to a terminal 3 and an emitter 26 connected to an output terminal 17. Transistor 12 and 22 are alternately saturated and rendered conducting by a biasing voltage E,, as shown in FIG. 2C, applied across a terminal 33 connected to emitters l6 and 26 of transistors 12 and 22, respectively, and a terminal 34 connected to a common connection between biasing resistors 41 and 43 connected to bases 20 and 30 of transistors 12 and 22, respectively. Biasing voltage E, is phase related to signal E, and as shown in FIGS. 2C and 2A, E is in phase with signal E,. v

Transistor 12 is saturated and conducts during positive half cycles of bias voltage E The low collector-emitter resistance of transistor 12 results in an insignificant voltage drop and positive half cycles of voltages E across resistor 5 are essentially provided to terminals I3, 17. Transistor 22 saturates and conducts during negative half cycles of bias voltage E The low collector-emitter. resistance of transistor 22 results in an insignificant voltage drop and negative half cycles of voltage E across resistor 6 are essentially provided to terminals 13, 17. Due to the connection of transistor 22, resistor 6 andterminals l3 and 17 the negative half cycles of voltage E, are inverted. Thus output E is composed essentially of the positive half-cyclesof voltage E and the inverted negative half-cycles of voltage E When signal E, and bias E, are in phase, transistor 22 has a forward current when conducting from collector 24 to emitter 26 due to voltage E Transistor 12, when conducting, has a reverse current from collector 18 to emitter 19 due to voltage E Similarly transistor 22 experiences a reverse current due to voltageE when signal E is I8Q out of-phase with bias E Since a reverse current will occur during operation of demodulator 1, care should be taken that the reverse current does not exceed the. reverse current capability of the particular type of transistor used. v

The reverse resistance between each emitter and collector is approximately equal to the forward resistance between each emitter and collector due to the saturation of transistor 12 or 22 by bias E Deinodula'tor 1 may be operated when signal E, is outof-phase with bias B; such' as shown in FIG. 2D. Output E will then be a negative full wave output shown in FIG. 2E.

The device of the present invention as heretofore described is a full wave phase sensitive demodulator in which an alternating current signal is divided into two alternating current voltages and half cycles of the two alternating current voltages are combined to provide a full wave demodulated output. The device of the present invention is a full wave phase sensitive demodulator using no reactive parts and having an unlimited frequency response and a fast response time.

What is claimed is:

l. A phase sensitive demodulator for converting an alternating current signal to a demodulated output, comprising:

means for dividing the alternating current signal into two al ternating current voltages;

a terminal common to both voltages;

an output terminal connected to the common terminal;

a second output terminal;

a pair of transistors having collector elements connected through the dividing means to the common terminal, emitter elements connected to the second output terminal and base elements;

means including an alternating current bias phase related to the two alternating current voltages connected across the across the output terminals -,in the other alternate half cycles when the other transistor conducts to provide a demodulated output across the output terminals corresponding in polarity to-the phaseof the alternating currentsignal.

a: a n m 

1. A phase sensitive demodulator for converting an alternating current signal to a demodulated output, comprising: means for dividing the alternating current signal into two alternating current voltages; a terminal common to both voltages; an output terminal connected to the common terminal; a second output terminal; a pair of transistors having collector elements connected through the dividing means to the common terminal, emitter elements connected to the second output terminal and base elements; means including an alternating current bias phase related to the two alternating current voltages connected across the emitter and base of each transistor for controlling conduction of the transistors; and the controlling means alternately rendering the transistors conducting in half cycles of the voltages providing an output across the output terminals in the alternate half cycles when one transistor conducts and for providing an output across the output terminals in the other alternate half cycles when the other transistor conducts to provide a demodulated output across the output terminals corresponding in polarity to the phase of the alternating current signal. 